The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2025

Filed:

Jun. 24, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Karthik Kumar, Chandler, AZ (US);

Francesc Guim Bernat, Barcelona, ES;

Mark A Schmisseur, Phoenix, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/12 (2016.01); G06F 1/3234 (2019.01); G06F 12/02 (2006.01); G06F 12/123 (2016.01); G06F 12/14 (2006.01);
U.S. Cl.
CPC ...
G06F 12/123 (2013.01); G06F 1/3275 (2013.01); G06F 12/023 (2013.01); G06F 12/1466 (2013.01); G06F 2212/1052 (2013.01);
Abstract

The platform data aging for adaptive memory scaling described herein provides technical solutions for technical problems facing power management for electronic device processors. Technical solutions described herein include improved processor power management based on a memory region life-cycle (e.g., short-lived, long-lived, static). In an example, a short-term memory request is allocated to a short-term memory region, and that short-term memory region is powered down upon expiration of the lifetime of all short-term memory requests on the short-term memory region. Multiple memory regions may be scaled down (e.g., shut down) or scaled up based on demands for memory capacity and bandwidth.


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