The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2025

Filed:

Feb. 29, 2024
Applicant:

Rambus Inc., San Jose, CA (US);

Inventors:

Frederick A Ware, Los Altos Hills, TX (US);

Robert E. Palmer, Chapel Hill, CA (US);

John W. Poulton, Chapel Hill, NC (US);

Andrew M. Fuller, Durham, NC (US);

Assignee:

Rambus Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2019.01); G06F 1/12 (2006.01); G06F 1/3225 (2019.01); G06F 1/3237 (2019.01); G06F 1/324 (2019.01); G06F 3/06 (2006.01); G06F 13/16 (2006.01); G11C 7/04 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 11/4076 (2006.01); G11C 11/4096 (2006.01); G06F 9/38 (2018.01); G06F 12/0855 (2016.01); G06F 13/36 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3237 (2013.01); G06F 1/12 (2013.01); G06F 1/3225 (2013.01); G06F 1/324 (2013.01); G06F 3/0604 (2013.01); G06F 3/0625 (2013.01); G06F 3/0629 (2013.01); G06F 3/0673 (2013.01); G06F 13/1689 (2013.01); G11C 7/04 (2013.01); G11C 7/10 (2013.01); G11C 7/1051 (2013.01); G11C 7/1066 (2013.01); G11C 7/1072 (2013.01); G11C 7/1078 (2013.01); G11C 7/109 (2013.01); G11C 7/1093 (2013.01); G11C 7/22 (2013.01); G11C 7/222 (2013.01); G11C 7/225 (2013.01); G11C 11/4076 (2013.01); G11C 11/4096 (2013.01); G06F 9/3836 (2013.01); G06F 12/0857 (2013.01); G06F 13/36 (2013.01); G06F 2201/88 (2013.01); G11C 2207/2254 (2013.01); Y02D 10/00 (2018.01);
Abstract

A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.


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