The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2025

Filed:

Dec. 15, 2023
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Fatma Arzum Simsek-Ege, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 88/00 (2025.01); G11C 5/06 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 88/00 (2025.01); G11C 5/06 (2013.01); H01L 23/5384 (2013.01); H01L 23/5386 (2013.01); H01L 25/0657 (2013.01); H10D 84/0165 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01);
Abstract

Methods, systems, and devices for transistor configurations for multi-deck memory devices are described. A memory device may include a first set of transistors formed in part by doping portions of a first semiconductor substrate of the memory device. The memory device may include a set of memory cells arranged in a stack of decks of memory cells above the first semiconductor substrate and a second semiconductor substrate bonded above the stack of decks. The memory device may include a second set of transistors formed in part by doping portions of the second semiconductor substrate. The stack of decks may include a lower set of one or more decks that is coupled with the first set of transistors and an upper set of one or more decks that is coupled with the second set of transistors.


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