The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2025

Filed:

Oct. 11, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yi-Chen Lo, Zhubei, TW;

Li-Te Lin, Hsinchu, TW;

Yu-Lien Huang, Jhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/01 (2025.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 21/768 (2006.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 64/27 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 62/40 (2025.01); H10D 64/62 (2025.01);
U.S. Cl.
CPC ...
H10D 30/024 (2025.01); H01L 21/02164 (2013.01); H01L 21/02211 (2013.01); H01L 21/02274 (2013.01); H01L 21/31144 (2013.01); H01L 21/32139 (2013.01); H01L 21/76802 (2013.01); H01L 21/7685 (2013.01); H01L 21/76879 (2013.01); H10D 62/151 (2025.01); H10D 64/017 (2025.01); H10D 64/021 (2025.01); H10D 64/511 (2025.01); H10D 84/0147 (2025.01); H10D 84/038 (2025.01); H10D 62/40 (2025.01); H10D 64/62 (2025.01); H10D 84/0149 (2025.01); H10D 84/0151 (2025.01); H10D 84/0158 (2025.01);
Abstract

A method for fabricating a semiconductor device comprises forming a gate electrode structure over a first region of a semiconductor substrate, and forming a source/drain region on a second region of the semiconductor substrate. The gate electrode structure comprises a metal gate electrode layer, a gate dielectric layer, and gate sidewalls. The second region of the semiconductor substrate is on an opposing side of the metal gate electrode layer. The method for fabricating a semiconductor device further comprises forming an interlayer dielectric layer over the source/drain regions and the gate sidewall, and forming an oxide layer over the source/drain region and the gate sidewall without substantially forming the second oxide layer on the gate electrode layer.


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