Low jitter clock multiplier circuit and method with arbitrary frequency acquisition

Abstract

A circuit and method are described for generating a low jitter output clock having an arbitrary non-integer divide ratio relative to a high-frequency clock. Integer divide ratios of the high-frequency clock may be achieved by dividing the high-frequency clock by the reference clock and phase locking the output clock to the high-frequency clock. Non-integer divide ratios can be achieved by dividing the high-frequency clock by the nearest integer, rounded down, and then delaying the resultant output clock by the modulus of the division. The delay can then be rotated across to create a clock with a non-integer divide ratio relative to the high-frequency clock. By doing so, a high-frequency clock may be used that is not constrained by having a frequency that is an integer multiple of each desired component-specific output clock signal.