Adaptive cyclic delay line for fractional-n pll

Abstract

Embodiments herein relate to a phase-locked loop (PLL) circuit which compensates for varying delays in a feedback clock signal which are caused by the use of fractional division. In one aspect, a delay circuit is used to provide progressively larger delays for the feedback clock signal within each division cycle, when the divider uses the smaller divisor, N. This compensates for the associated larger frequency and smaller clock cycle, compared to when the divisor is N+1. Additionally, the delays introduced by the delay circuit can be controlled by an adaptive gain circuit. The adaptive gain circuit samples a phase error of a phase detector of the PLL to determine whether to increase or decreases the gain, thereby increasing or decreasing, respectively, the delay.