The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 20, 2025
Filed:
Dec. 11, 2023
Kepler Computing Inc., San Francisco, CA (US);
Sasikanth Manipatruni, Portland, OR (US);
Yuan-Sheng Fang, Oakland, CA (US);
Robert Menezes, Portland, OR (US);
Rajeev Kumar Dokania, Beaverton, OR (US);
Gaurav Thareja, Santa Clara, CA (US);
Amrita Mathuriya, Portland, OR (US);
Ramamoorthy Ramesh, Moraga, CA (US);
Kepler Computing Inc., San Francisco, CA (US);
Abstract
A new class of multiplier cells (analog or digital) is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from first and second majority gates. The multiplier cell can also be implemented with a combination of two majority gates with majority and AND functions integrated in each of them. The two majority gates are coupled. Each of the first and second majority logic gates comprise a capacitor with non-linear polar material. The first and second majority gates receive the two inputs A and B that are to be multiplied. Other inputs received by the first and second majority gates are carry-in input, a sum-in input, and a bias voltage. The bias voltage is a negative voltage, which produces an integrated AND function in conjunction with a majority function. The second majority gate receives additional inputs, which are inverted output of the first majority gate.