The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2025

Filed:

Aug. 26, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kaladhar Radhakrishnan, Chandler, AZ (US);

Krishna Bharath, Phoenix, AZ (US);

William J. Lambert, Chandler, AZ (US);

Adel A. Elsherbini, Tempe, AZ (US);

Sriram Srinivasan, Chandler, AZ (US);

Christopher Schaef, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 24/73 (2013.01); H01L 25/0652 (2013.01); H01L 25/50 (2013.01); H01L 23/3128 (2013.01); H01L 23/3185 (2013.01); H01L 23/481 (2013.01); H01L 24/08 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/33 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/33181 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73253 (2013.01); H01L 2924/1427 (2013.01); H01L 2924/19011 (2013.01); H01L 2924/19015 (2013.01); H01L 2924/19042 (2013.01);
Abstract

A microelectronic assembly is provided comprising a first integrated circuit (IC) die having an electrical load circuit, a second IC die having a portion of a voltage regulator (VR), and a third IC die comprising inductors of the VR. The third IC die is between the first IC die and the second IC die, and the VR receives power at a first voltage and provides power at a second voltage to the electrical load circuit, the second voltage being lower than the first voltage. In various embodiments, the inductors in the third IC die comprise magnetic thin films. The third IC die may be a passive die without any active elements in some embodiments. In some embodiments, the microelectronic assembly further comprises a package substrate having conductive pathways, and the second IC die is between the third IC die and the package substrate.


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