The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 20, 2025
Filed:
Nov. 24, 2023
Applicant:
Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;
Inventors:
Te-An Chen, Taichung, TW;
Meng-Han Lin, Hsinchu, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu, TW;
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); B65D 83/141 (2025.01); H01L 21/765 (2006.01); H10D 12/01 (2025.01); H10D 18/60 (2025.01); H10D 30/01 (2025.01); H10D 48/07 (2025.01); H10D 62/00 (2025.01); H10D 62/17 (2025.01); H10D 64/00 (2025.01); H10D 64/01 (2025.01); H10D 84/00 (2025.01); H10D 84/83 (2025.01); H10D 84/90 (2025.01); H10F 77/00 (2025.01);
U.S. Cl.
CPC ...
H01L 21/76224 (2013.01); H01L 21/765 (2013.01); H10D 62/021 (2025.01); H10D 64/01 (2025.01); H10D 64/115 (2025.01); H10D 84/83 (2025.01);
Abstract
The present disclosure provides a semiconductor device, including a substrate, a first active region in the substrate, a second active region in the substrate and adjacent to the first active region, an isolation region in the substrate and between the first active region and the second active region, and a dummy gate overlapping with the isolation region, wherein an entire bottom width of the dummy gate is greater than an entire top width of the isolation region.