The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2025

Filed:

Jun. 10, 2022
Applicant:

Parabellum Strategic Opportunities Fund Llc, Wilmington, DE (US);

Inventors:

Chih Wei Lu, Hsinchu, TW;

Chung-Ju Lee, Hsinchu, TW;

Hai-Ching Chen, Hsinchu, TW;

Chien-Hua Huang, Miaoli County, TW;

Tien-I Bao, Taoyuan County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 21/768 (2006.01); H01L 23/485 (2006.01); H01L 29/49 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28132 (2013.01); H01L 21/28088 (2013.01); H01L 21/76832 (2013.01); H01L 21/76834 (2013.01); H01L 21/76895 (2013.01); H01L 21/76897 (2013.01); H01L 23/485 (2013.01); H01L 29/4966 (2013.01); H01L 29/78 (2013.01);
Abstract

A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.


Find Patent Forward Citations

Loading…