The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2025

Filed:

Jul. 02, 2024
Applicant:

Atomera Incorporated, Los Gatos, CA (US);

Inventor:

Hideki Takeuchi, San Jose, CA (US);

Assignee:

ATOMERA INCORPORATED, Los Gatos, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/27 (2023.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/322 (2006.01); H10B 41/35 (2023.01); H10B 43/27 (2023.01); H10D 62/815 (2025.01); H10D 64/68 (2025.01);
U.S. Cl.
CPC ...
H01L 21/02507 (2013.01); H01L 21/28079 (2013.01); H01L 21/3221 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/27 (2023.02); H10D 62/8162 (2025.01); H10D 64/685 (2025.01);
Abstract

A method for making a semiconductor device may include forming a superlattice gettering layer on a substrate. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include forming a memory device above the superlattice gettering layer including a metal induced crystallization (MIC) channel adjacent the semiconductor substrate, and a gate associated with the MIC channel. The superlattice gettering layer may further include gettered metal particles from the MIC channel.


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