The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2025

Filed:

Apr. 30, 2024
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

William C. Filipiak, Northville, MI (US);

Elancheren Durai, Boise, ID (US);

Quincy R. Holton, Kuna, ID (US);

Adam Satar, Northville, MI (US);

Brett Hunter, White Lake, MI (US);

David R. Silwanowicz, Macomb, MI (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G06F 3/06 (2006.01); G11C 7/04 (2006.01); G11C 11/406 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 7/04 (2013.01); G11C 11/40626 (2013.01); G11C 16/3418 (2013.01);
Abstract

Methods, apparatuses and systems related to managing deck-specific read levels are described. The apparatus may include a memory array having the memory cells organized into two or more decks. The apparatus can determine a delay between programming the decks. The apparatus can derive and implement the deck-specific read levels by selectively adjusting a base read level with an offset level according to the delay and/or the targeted read location.


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