The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2025

Filed:

May. 22, 2024
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Joydeep Ray, Folsom, CA (US);

Altug Koker, El Dorado Hills, CA (US);

Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US);

Michael Macpherson, Portland, OR (US);

Aravindh V. Anantaraman, Folsom, CA (US);

Vasanth Ranganathan, El Dorado Hills, CA (US);

Lakshminarayanan Striramassarma, Folsom, CA (US);

Varghese George, Folsom, CA (US);

Abhishek Appu, El Dorado Hills, CA (US);

Prasoonkumar Surti, Folsom, CA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/50 (2006.01); G06T 1/20 (2006.01); G06T 1/60 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1605 (2013.01); G06F 9/3004 (2013.01); G06F 9/3887 (2013.01); G06F 9/3888 (2023.08); G06F 9/38885 (2023.08); G06F 9/5016 (2013.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01);
Abstract

An apparatus to facilitate efficient data sharing for graphics data processing operations is disclosed. The apparatus includes a processing resource to generate a stream of instructions, an L1 cache communicably coupled to the processing resource and comprising an on-page detector circuit to determine that a set of memory requests in the stream of instructions access a same memory page; and set a marker in a first request of the set of memory requests; and arbitration circuitry communicably coupled to the L1 cache, the arbitration circuitry to route the set of memory requests to memory comprising the memory page and to, in response to receiving the first request with the marker set, remain with the processing resource to process the set of memory requests.


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