The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2025

Filed:

Apr. 08, 2023
Applicant:

Sambanova Systems, Inc., Palo Alto, CA (US);

Inventors:

Darshan Gandhi, Palo Alto, CA (US);

Manish K. Shah, Austin, TX (US);

Raghu Prabhakar, San Jose, CA (US);

Gregory Frederick Grohoski, Bee Cave, TX (US);

Youngmoon Choi, Milpitas, CA (US);

Jinuk Shin, San Jose, CA (US);

Assignee:

SambaNova Systems, Inc., Palo Alto, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/30 (2006.01); G01R 31/27 (2006.01); G06F 1/08 (2006.01); G06F 1/28 (2006.01); G06F 1/324 (2019.01);
U.S. Cl.
CPC ...
G06F 1/305 (2013.01); G01R 31/275 (2013.01); G06F 1/08 (2013.01); G06F 1/28 (2013.01); G06F 1/324 (2013.01);
Abstract

A method includes analyzing a dataflow graph to generate configuration information loadable into an integrated circuit. The dataflow graph specifies operations to be performed and data dependencies between the operations. The configuration information is usable by the integrated circuit to configure compute units of the integrated circuit to perform respective one or more of the operations of the dataflow graph, control data flow between the compute units to accomplish the data dependencies between the respective operations performed by the compute units, and control when each compute unit starts to perform the respective operations on the data to mitigate supply voltage droop caused by a time rate of change of current drawn by the integrated circuit through inductive loads of the integrated circuit.


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