The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2025

Filed:

Dec. 06, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Vikrant Thigle, Bangalore, IN;

Vijay Anand Mathiyalagan, Austin, TX (US);

Anand Haridass, Karnataka, IN;

Arun Chandrasekhar, Bangalore, IN;

Gerald Pasdast, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 19/25 (2006.01); G01R 19/00 (2006.01); G05F 1/46 (2006.01);
U.S. Cl.
CPC ...
G01R 19/0038 (2013.01); G01R 19/25 (2013.01); G05F 1/46 (2013.01);
Abstract

Embodiments herein relate to a chiplet or other die which includes multiple sense points within the die and components for digitizing and outputting sensed voltages of the sense points. In one approach, an analog-to-digital converter (ADC) is coupled to each sense point, and a multiplexer is coupled to the outputs of the ADCs. A select signal for the multiplexer can be received from an external control unit which selects one of the sense points based on information such as a current workflow of the die. The selected sense point can change as the workflow changes. The optimal sense point can be determined by comparing the voltage of each sense point and selecting the sense point with the lowest voltage. The sensed voltage is provided to a voltage regulator as a feedback signal to optimize control of the power supply of the die.


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