The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 13, 2025

Filed:

Aug. 04, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Chia-Cheng Ho, Hsinchu, TW;

Ming-Ta Lei, Hsin-Chu, TW;

Yu-Chang Jong, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/00 (2025.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10D 30/01 (2025.01); H10D 30/65 (2025.01); H10D 64/01 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10D 64/111 (2025.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10D 30/0281 (2025.01); H10D 30/655 (2025.01); H10D 64/01 (2025.01); H10D 84/83 (2025.01);
Abstract

Various embodiments of the present disclosure are directed towards an integrated chip including a field plate. A gate structure overlies a substrate between a source region and a drain region. A drift region is disposed laterally between the gate structure and the drain region. A first dielectric layer overlies the substrate. A field plate is disposed within the first dielectric layer between the gate structure and the drain region. A conductive wire overlies the first dielectric layer and contacts the field plate. At least a portion of the conductive wire directly overlies a first sidewall of the drift region.


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