The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 13, 2025

Filed:

Aug. 07, 2022
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventor:

Linggang Fang, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 1/68 (2025.01); H10D 1/00 (2025.01); H10D 1/66 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H10D 1/684 (2025.01); H10D 1/042 (2025.01); H10D 1/68 (2025.01); H10D 1/692 (2025.01); H10D 1/716 (2025.01); H10D 1/665 (2025.01); H10D 64/035 (2025.01);
Abstract

A method for forming a poly-insulator-poly (PIP) capacitor is disclosed. A semiconductor substrate having a capacitor forming region is provided. A first capacitor dielectric layer is formed on the capacitor forming region. A first poly electrode is formed on the first capacitor dielectric layer. A second capacitor dielectric layer is formed on the first poly electrode. A second poly electrode is formed on the second capacitor dielectric layer. A third poly electrode is formed adjacent to a first sidewall of the second poly electrode. A third capacitor dielectric layer is formed between the third poly electrode and the second poly electrode. A fourth poly electrode is formed adjacent to a second sidewall of the second poly electrode that is opposite to the first sidewall. A fourth capacitor dielectric layer is formed between the fourth poly electrode and the second poly electrode.


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