The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 13, 2025
Filed:
Mar. 08, 2022
Applicant:
Synopsys, Inc., Mountain View, CA (US);
Inventors:
Assignee:
Synopsys, Inc., Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/225 (2006.01); H01L 21/027 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H10D 30/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H01L 21/2253 (2013.01); H01L 21/0274 (2013.01); H01L 21/265 (2013.01); H01L 21/26513 (2013.01); H01L 21/266 (2013.01); H10D 30/0241 (2025.01); H10D 84/0151 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01); H10D 84/0128 (2025.01);
Abstract
A configuration to isolate ion implantation of silicon channels for placement of integrated circuit devices within an integrated circuit layout. The configuration layers a photolithographic mask having one or more openings on a silicon substrate. The configuration directs a focused ion beam towards the silicon substrate to implant ions in the silicon substrate at the one or more openings in the photolithographic mask. The configuration anneals the silicon substrate with the layered photolithographic mask to activate a reaction between silicon of the silicon substrate and the implanted ion to achieve an ionized formation in the silicon substrate.