The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 13, 2025

Filed:

Mar. 08, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Shenggao Li, Cupertino, CA (US);

Szu-Chun Tsao, Hsinchu, TW;

Wen-Shen Chou, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/3308 (2020.01); G06F 30/337 (2020.01); G06F 30/367 (2020.01); G06F 30/373 (2020.01); G06F 30/398 (2020.01); G06F 119/06 (2020.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 30/3308 (2020.01); G06F 30/337 (2020.01); G06F 30/367 (2020.01); G06F 30/373 (2020.01); G06F 2119/06 (2020.01);
Abstract

Systems and methods are provided for designing an integrated circuit device. In one example, a method for designing an integrated circuit device may include the operations of: receiving a schematic diagram of the integrated circuit device; generating, by a simulation program, a first transient simulation of the integrated circuit device based on the schematic diagram; determining from the first transient simulation of the integrated circuit device a plurality of maximum voltage change values between conductor networks (nets) within the schematic diagram of the integrated circuit device; storing the plurality of maximum voltage change values for the schematic diagram of the integrated circuit device in a computer readable medium; and utilizing, by a layout program, the stored plurality of maximum voltage change values to generate a layout design for the integrated circuit device according to one or more high voltage design constraints. In embodiments, the plurality of maximum voltage change values are stored in the form of a matrix in an extensible markup language (XML) file.


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