The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 06, 2025

Filed:

Aug. 10, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Mattia Robustelli, Milan, IT;

Innocenzo Tortorelli, Cernusco sul Naviglio, IT;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 63/00 (2022.12); H10N 70/00 (2022.12); H10N 70/20 (2022.12);
U.S. Cl.
CPC ...
H10B 63/845 (2023.01); H10N 70/066 (2023.01); H10N 70/231 (2023.01); H10N 70/841 (2023.01); H10N 70/882 (2023.01);
Abstract

Methods, systems, and devices for asymmetric memory cell design are described. A memory device may implement a programming scheme that uses low programming pulses based on an asymmetric memory cell design. For example, the asymmetric memory cells may have electrodes with different contact areas (e.g., widths) and may accordingly be biased to a desired polarity (e.g., negative biased or positive biased) for programming operations. That is, the asymmetric memory cell design may enable an asymmetric read window budget. For example, an asymmetric memory cell may be polarity biased, supporting programming operations for logic states based on the polarity bias.


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