The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 06, 2025

Filed:

Feb. 25, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Minjung Kim, Cheonan-si, KR;

Dongkyu Kim, Anyang-si, KR;

Jongyoun Kim, Seoul, KR;

Seokhyun Lee, Hwaseong-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2022.12); H01L 23/00 (2005.12); H01L 23/48 (2005.12); H01L 23/498 (2005.12); H01L 25/10 (2005.12);
U.S. Cl.
CPC ...
H01L 25/0657 (2012.12); H01L 23/481 (2012.12); H01L 23/49816 (2012.12); H01L 23/49822 (2012.12); H01L 24/06 (2012.12); H01L 24/16 (2012.12); H01L 24/17 (2012.12); H01L 24/81 (2012.12); H01L 25/105 (2012.12); H01L 2224/0401 (2012.12); H01L 2224/06181 (2012.12); H01L 2224/16146 (2012.12); H01L 2224/16235 (2012.12); H01L 2224/17181 (2012.12); H01L 2225/06517 (2012.12); H01L 2924/3511 (2012.12);
Abstract

A semiconductor package includes a first redistribution substrate, a lower semiconductor chip on the first redistribution substrate and a through via therein, a first lower conductive structure and a second lower conductive structure that are on the first redistribution substrate and are laterally spaced apart from the lower semiconductor chip, an upper semiconductor chip on the lower semiconductor chip and the second lower conductive structure and coupled to the through via and the second lower conductive structure, and an upper conductive structure on the first lower conductive structure. A width of the second lower conductive structure is greater than a width of the through via.


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