The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 06, 2025

Filed:

Jul. 21, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chih-Chia Hu, Taipei, TW;

Ming-Fa Chen, Taichung, TW;

Sung-Feng Yeh, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2022.12); H01L 21/683 (2005.12); H01L 23/00 (2005.12); H01L 25/00 (2005.12);
U.S. Cl.
CPC ...
H01L 25/0652 (2012.12); H01L 21/6835 (2012.12); H01L 23/562 (2012.12); H01L 24/08 (2012.12); H01L 24/80 (2012.12); H01L 25/50 (2012.12); H01L 2221/68354 (2012.12); H01L 2224/08145 (2012.12); H01L 2224/80895 (2012.12); H01L 2224/80896 (2012.12); H01L 2225/06513 (2012.12); H01L 2225/06524 (2012.12); H01L 2225/06548 (2012.12); H01L 2225/06586 (2012.12); H01L 2924/3511 (2012.12);
Abstract

Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes an integrated circuit structure, a first die stack and a dummy die. The first die stack includes a plurality of first die structures and is bonded to the integrated circuit structure at a first side of the first die stack. The dummy die includes a plurality of through substrate vias, is located aside the first die stack and is electrically connected to the integrated circuit structure at the first side of the first die stack. In some embodiments, the height of the through substrate vias of the dummy die is the same as the height of the first die stack.


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