The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 06, 2025

Filed:

Aug. 07, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Pei-Yu Chou, Hsinchu, TW;

Tze-Liang Lee, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2005.12); H01L 21/311 (2005.12); H01L 21/768 (2005.12); H01L 27/088 (2005.12); H01L 29/40 (2005.12); H01L 29/417 (2005.12); H01L 29/66 (2005.12);
U.S. Cl.
CPC ...
H01L 21/28247 (2012.12); H01L 21/76802 (2012.12); H01L 21/76816 (2012.12); H01L 29/401 (2012.12); H01L 29/66454 (2012.12); H01L 29/66545 (2012.12); H01L 29/66795 (2012.12); H01L 21/31116 (2012.12); H01L 21/76832 (2012.12); H01L 21/76834 (2012.12); H01L 27/0886 (2012.12); H01L 29/41791 (2012.12);
Abstract

A method includes forming a dummy gate stack on a semiconductor fin, forming gate spacers on sidewalls of the dummy gate stack, forming a first inter-layer dielectric, with the gate spacers and the dummy gate stack being in the first inter-layer dielectric, removing the dummy gate stack to form a trench between the gate spacers, forming a replacement gate stack in the trench, and depositing a dielectric capping layer. A bottom surface of the dielectric capping layer contacts a first top surface of the replacement gate stack and a second top surface of the first inter-layer dielectric. A second inter-layer dielectric is deposited over the dielectric capping layer. A source/drain contact plug is formed and extends into the second inter-layer dielectric, the dielectric capping layer, and the first inter-layer dielectric.


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