The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 06, 2025

Filed:

Jul. 26, 2023
Applicant:

Marvell Asia Pte Ltd, Singapore, SG;

Inventors:

Nikhil Bernard John Stephen, Sunnyvale, CA (US);

Senad Durakovic, Palo Alto, CA (US);

Chien-Chun Chou, Morgan Hill, CA (US);

Pranav Jonnalagadda, San Jose, CA (US);

Ulf Hanebutte, Gig Harbor, WA (US);

Assignee:

Marvell Asia Pte Ltd, Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 8/41 (2017.12);
U.S. Cl.
CPC ...
G06F 8/453 (2012.12); G06F 8/443 (2012.12); G06F 8/451 (2012.12);
Abstract

A method includes receiving a machine learning (ML) network model in high-level code; generating an internal representation (IR), the IR is mapped to components in a multi-processing tile device; determining whether a first processing tile with a first on-chip memory (OCM) has a same dimension for an input/output tensor data as a second processing tile with a second OCM performing a same primitive function based on the IR; allocating a same memory address range within the first and the second OCM for the same primitive function if the first processing tile has the same dimension for the input/output tensor data as the second processing tile for the same primitive function; linking the memory address range of the first OCM to the memory address range of the second OCM to form a grouped memory space within the first and the second OCM respectively; and compiling low-level instructions based on the linking.


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