Partitioning a circuit for distributed balanced independent simulation jobs with upper-bounded memory

Abstract

Disclosed herein are system, method, and computer program product embodiments for partitioning large circuits into balanced portions for independent simulation. Embodiments include generating a reduced graph by removing a plurality of startpoint vertices from a graph corresponding to a circuit. A plurality of small weakly connected components (SWCCs) and a plurality of large weakly connected components (LWCCs) corresponding to the reduced graph are computed. A first plurality of balanced subgraphs based on the plurality of SWCCs, and a second plurality of balanced subgraphs based on the plurality of LWCCs, where each balanced subgraph of the first and second plurality of balanced subgraphs can be simulated using a simulator with a processing capacity less than or equal to a memory limit are generated. The first and the second plurality of balanced subgraphs are simulated.