The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 29, 2025
Filed:
Jun. 21, 2023
Applicant:
Parabellum Strategic Opportunities Fund Llc, Wilmington, DE (US);
Inventors:
Assignee:
Parabellum Strategic Opportunities Fund LLC, Austin, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/65 (2024.12); H01L 21/76 (2005.12); H01L 21/762 (2005.12); H10D 30/01 (2024.12); H10D 30/60 (2024.12); H10D 62/10 (2024.12); H10D 64/27 (2024.12);
U.S. Cl.
CPC ...
H10D 30/658 (2024.12); H01L 21/76 (2012.12); H01L 21/762 (2012.12); H10D 30/0289 (2024.12); H10D 30/603 (2024.12); H10D 62/116 (2024.12); H10D 64/516 (2024.12); H10D 64/518 (2024.12);
Abstract
A process for fabricating a semiconductor structure is disclosed. The process includes: forming an isolation trench in a substrate; forming a trench fill layer to at least fill the isolation trench in the substrate, the silicon oxide trench fill layer comprising a portion in contact with the substrate below an upper surface of the substrate; exposing a sidewall of the isolation trench and without exposing a bottom of the isolation trench in the substrate; and forming a gate structure over the substrate, wherein the gate structure contacts the sidewall of the isolation trench.