The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 29, 2025

Filed:

Jul. 10, 2023
Applicant:

Ememory Technology Inc., Hsinchu, TW;

Inventors:

Lun-Chun Chen, Hsinchu County, TW;

Ping-Lung Ho, Hsinchu County, TW;

Assignee:

EMEMORY TECHNOLOGY INC., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/02 (2005.12); G11C 16/24 (2005.12); G11C 16/26 (2005.12); G11C 17/16 (2005.12); H01L 23/00 (2005.12); H02H 9/02 (2005.12); H10B 20/25 (2022.12);
U.S. Cl.
CPC ...
H10B 20/25 (2023.01); G11C 16/24 (2012.12); G11C 16/26 (2012.12); G11C 17/16 (2012.12); H01L 23/576 (2012.12); H02H 9/02 (2012.12);
Abstract

An OTP memory cell includes an antifuse transistor, a first transistor and a second transistor. The antifuse transistor includes a first fin, a second fin, a first gate structure, a first drain/source contact layer and a second drain/source contact layer. A central region of the first fin and a central region of the second fin are covered by a first gate structure. The first drain/source contact layer is electrically connected with a first terminal of the first fin and a first terminal of the second fin. The second drain/source contact layer is electrically connected with a second terminal of the second fin but not electrically connected with a second terminal of the first fin. The first transistor is connected with the first drain/source contact layer. The second transistor is connected with the second drain/source contact layer.


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