The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 29, 2025

Filed:

Sep. 24, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Carlos Nava Rodriguez, Folsom, CA (US);

Yoav Harel, Carmichael, CA (US);

Joydeep Ray, Folsom, CA (US);

Abhishek R. Appu, El Dorado Hills, CA (US);

Vamsee Vardhan Chivukula, Folsom, CA (US);

Benjamin R. Pletcher, Mather, CA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 1/20 (2005.12); G06F 13/16 (2005.12); G06T 1/60 (2005.12); G06T 15/00 (2010.12);
U.S. Cl.
CPC ...
G06T 15/005 (2012.12); G06F 13/1673 (2012.12); G06T 1/20 (2012.12); G06T 1/60 (2012.12); G06T 2200/28 (2012.12);
Abstract

Dynamic routing of texture-load in graphics processing is described. An example of a processor includes one or more processing resources, the one or more processing resources to load a message including a texture load; a texture sampler and a data port; and a message router to route the texture load to a destination, wherein the destination may be either the texture sampler or the data port; wherein the message router includes arbitration circuitry to select the destination for the texture load, the arbitration circuitry to base selection of the destination at least in part on support by the data port for a format of a memory surface for the texture load; and a utilization metric for the data port representing availability of the data port.


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