The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 29, 2025
Filed:
Nov. 29, 2022
Applicant:
Rambus Inc., San Jose, CA (US);
Inventors:
Joohee Kim, Sunnyvale, CA (US);
Dongyun Lee, Sunnyvale, CA (US);
Assignee:
Rambus Inc., San Jose, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4093 (2005.12); G06F 11/20 (2005.12); G11C 29/00 (2005.12); H01L 23/00 (2005.12); H01L 25/065 (2022.12);
U.S. Cl.
CPC ...
G06F 11/2028 (2012.12); G11C 29/816 (2012.12); H01L 24/16 (2012.12); H01L 24/32 (2012.12); H01L 25/0657 (2012.12); H01L 2224/32145 (2012.12); H01L 2225/06513 (2012.12); H01L 2225/06517 (2012.12); H01L 2924/15311 (2012.12);
Abstract
Described are memory systems and devices in which each memory die in a three-dimensional stack of memory dies includes drive and receive circuitry that can communicate data signals from the stack on behalf of all the memory dies in the stack. The drive and receive circuitry, if defective on one device in the stack, can be disabled and substituted with the drive and receive circuitry from another. The stack of memory dies can thus function despite a failure of drive or receive circuitry in one or more of the memory dies. Each memory die includes test circuitry to detect defective drive and receive circuitry.