The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 21, 2025
Filed:
Apr. 15, 2024
United Microelectronics Corp., Hsin-Chu, TW;
Hui-Lin Wang, Taipei, TW;
Yu-Ping Wang, Hsinchu, TW;
Chen-Yi Weng, New Taipei, TW;
Chin-Yang Hsieh, Tainan, TW;
Yi-Hui Lee, Taipei, TW;
Ying-Cheng Liu, Tainan, TW;
Yi-An Shih, Changhua County, TW;
I-Ming Tseng, Kaohsiung, TW;
Jing-Yin Jhang, Tainan, TW;
Chien-Ting Lin, Tainan, TW;
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Abstract
A semiconductor structure includes a substrate, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and filling the spaces between the memory stack structures, a first interconnecting structure through the second dielectric layer, wherein a top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures, a third dielectric layer on the second dielectric layer, and a plurality of second interconnecting structures through the third dielectric layer, the second dielectric layer and the insulating layer on the top surfaces of the memory stack structures to contact the top surfaces of the memory stack structures.