The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2025

Filed:

Feb. 14, 2023
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Caspar Leendertz, Munich, DE;

Markus Beninger-Bina, Grosshelfendorf, DE;

Matteo Dainese, Munich, DE;

Alice Pei-Shan Leendertz, Unterhaching, DE;

Christian Philipp Sandow, Haar, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2005.12); H01L 29/06 (2005.12); H01L 29/08 (2005.12); H01L 29/10 (2005.12); H01L 29/40 (2005.12); H01L 29/417 (2005.12); H01L 29/739 (2005.12);
U.S. Cl.
CPC ...
H01L 29/66348 (2012.12); H01L 29/0696 (2012.12); H01L 29/083 (2012.12); H01L 29/1095 (2012.12); H01L 29/404 (2012.12); H01L 29/407 (2012.12); H01L 29/417 (2012.12); H01L 29/7396 (2012.12); H01L 29/7397 (2012.12);
Abstract

A semiconductor device includes a transistor that has: a drift region of a first conductivity type in a semiconductor substrate having a first main surface; a body region of a second conductivity type between the drift region and the first main surface; a plurality of trenches in the first main surface and patterning the semiconductor substrate into a plurality of mesas including a first mesa and a plurality of dummy mesas, the plurality of trenches including an active trench and a plurality of dummy trenches arranged in a row; a gate electrode arranged in the active trench; and a source region of the first conductivity type in the first mesa. The first mesa is arranged adjacent to the active trench. A dummy mesa is arranged between each adjacent pair of the dummy trenches. The dummy mesas do not carry load current during an on-state of the transistor.


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