The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2025

Filed:

Jun. 24, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Pritesh P. Shah, Round Rock, TX (US);

Suresh Chemudupati, Austin, TX (US);

Alexander Gendler, Haifa, IL;

David Hunt, Meelick, IE;

Christopher M. Macnamara, Ballyclough, IE;

Ofer Nathan, Haifa, IL;

Adwait Purandare, Hillsboro, OR (US);

Ankush Varma, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/3287 (2018.12); G06F 1/3228 (2018.12); G06F 1/3296 (2018.12); G06F 9/50 (2005.12);
U.S. Cl.
CPC ...
G06F 1/3287 (2012.12); G06F 1/3228 (2012.12); G06F 1/3296 (2012.12); G06F 9/5094 (2012.12); Y02D 10/00 (2017.12);
Abstract

A hardware controller within a core of a processor is described. The hardware controller includes telemetry logic to generate telemetry data that indicates an activity state of the core; core stall detection logic to determine, based on the telemetry data from the telemetry logic, whether the core is in an idle loop state; and a power controller that, in response to the core stall detection logic determining that the core is in the idle loop state, is to decrease a power mode of the core from a first power mode associated with a first set of power settings to a second power mode associated with a second set of power settings.


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