The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2025

Filed:

Jan. 04, 2024
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Shaofeng Ding, Suwon-si, KR;

Jeong Hoon Ahn, Seongnam-si, KR;

Yun Ki Choi, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 10/00 (2022.12); H01L 21/02 (2005.12); H01L 21/8238 (2005.12); H01L 27/092 (2005.12); H01L 29/06 (2005.12); H01L 29/08 (2005.12); H01L 29/417 (2005.12); H01L 29/423 (2005.12); H01L 29/66 (2005.12); H01L 29/78 (2005.12); H01L 29/786 (2005.12); H10B 12/00 (2022.12);
U.S. Cl.
CPC ...
H10B 10/18 (2023.01); H01L 21/0259 (2012.12); H01L 21/823807 (2012.12); H01L 21/823814 (2012.12); H01L 21/823821 (2012.12); H01L 21/823871 (2012.12); H01L 27/092 (2012.12); H01L 29/0665 (2012.12); H01L 29/0847 (2012.12); H01L 29/41733 (2012.12); H01L 29/41791 (2012.12); H01L 29/42392 (2012.12); H01L 29/66545 (2012.12); H01L 29/66742 (2012.12); H01L 29/66795 (2012.12); H01L 29/7851 (2012.12); H01L 29/78618 (2012.12); H01L 29/78696 (2012.12); H10B 12/50 (2023.01);
Abstract

A semiconductor device includes a substrate including a logic cell region and a connection region, a dummy transistor on the connection region, an intermediate connection layer on the dummy transistor, the intermediate connection layer including a connection pattern electrically connected to the dummy transistor, a first metal layer on the intermediate connection layer, an etch stop layer between the intermediate connection layer and the first metal layer, the etch stop layer covering a top surface of the connection pattern, and a penetration contact extended from the first metal layer toward a bottom surface of the substrate penetrating the connection region.


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