Delay circuit and memory

Abstract

A delay circuit includes a self-shielding circuit and a delay. The self-shielding circuit is configured to: receive an initial command signal and N initial clock signals, register the initial command signal according to a first initial clock signal among the N initial clock signals that triggers the initial command signal at earliest, shield other N−1 second initial clock signals, and output N intermediate command signals, where N is an integer greater than or equal to 2, and the N initial clock signals have a same frequency and different phases. The delay is electrically connected to the self-shielding circuit and is configured to: receive the N intermediate command signals and the N initial clock signals, and delay and output the N intermediate command signals to obtain a delayed command signal. Thus, the accuracy of signal processing can be improved.