The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2025

Filed:

Apr. 16, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Shu-Han Chen, Hsinchu, TW;

Tsung-Ju Chen, Hsinchu, TW;

Chun-Heng Chen, Hsinchu, TW;

Chi On Chui, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2005.12); H01L 21/02 (2005.12); H01L 21/306 (2005.12); H01L 21/311 (2005.12); H01L 21/3115 (2005.12); H01L 29/66 (2005.12); H01L 29/78 (2005.12); H01L 21/265 (2005.12); H01L 29/10 (2005.12);
U.S. Cl.
CPC ...
H01L 29/0673 (2012.12); H01L 21/0262 (2012.12); H01L 21/30604 (2012.12); H01L 21/31116 (2012.12); H01L 21/31155 (2012.12); H01L 29/66545 (2012.12); H01L 29/66795 (2012.12); H01L 29/785 (2012.12); H01L 21/26513 (2012.12); H01L 29/1083 (2012.12);
Abstract

In an embodiment, a structure includes: a nano-structure; an epitaxial source/drain region adjacent the nano-structure; a gate dielectric wrapped around the nano-structure; a gate electrode over the gate dielectric, the gate electrode having an upper portion and a lower portion, a first width of the upper portion increasing continually in a first direction extending away from a top surface of the nano-structure, a second width of the lower portion being constant along the first direction; and a gate spacer between the gate dielectric and the epitaxial source/drain region.


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