The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2025

Filed:

Aug. 07, 2022
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Sheng Zhang, Singapore, SG;

Kai Zhu, Singapore, SG;

Chien-Kee Pang, Singapore, SG;

Chia-Liang Liao, Yunlin County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2005.12); H01L 21/02 (2005.12); H01L 23/00 (2005.12);
U.S. Cl.
CPC ...
H01L 24/80 (2012.12); H01L 21/02337 (2012.12); H01L 2224/80895 (2012.12); H01L 2224/80896 (2012.12);
Abstract

Provided is a manufacturing method of a semiconductor structure. The manufacturing method includes the following steps. A first dielectric layer is formed on a first substrate. A second dielectric layer is formed on a second substrate. A first heat treatment is performed on the first dielectric layer and the second dielectric layer, wherein a temperature of the first heat treatment is between 300° C. and 400° C. A first conductive via is formed in the first dielectric layer. A second conductive via is formed in the second dielectric layer. The first substrate and the second substrate are bonded in a manner that the first dielectric layer faces the second dielectric layer, so as to connect the first conductive via and the second conductive via.


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