The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2025

Filed:

Dec. 15, 2023
Applicant:

Avalanche Technology, Inc., Fremont, CA (US);

Inventors:

Zihui Wang, Mountain View, CA (US);

Yiming Huai, Pleasanton, CA (US);

Assignee:

Avalanche Technology, Inc., Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/552 (2005.12); H01L 23/00 (2005.12); H01L 23/498 (2005.12); H01L 25/065 (2022.12); H10B 80/00 (2022.12);
U.S. Cl.
CPC ...
H01L 23/552 (2012.12); H01L 23/49822 (2012.12); H01L 24/16 (2012.12); H01L 24/32 (2012.12); H01L 24/48 (2012.12); H01L 24/73 (2012.12); H01L 25/0657 (2012.12); H10B 80/00 (2023.01); H01L 24/17 (2012.12); H01L 24/33 (2012.12); H01L 2224/16146 (2012.12); H01L 2224/16227 (2012.12); H01L 2224/17181 (2012.12); H01L 2224/32145 (2012.12); H01L 2224/32225 (2012.12); H01L 2224/33181 (2012.12); H01L 2224/48091 (2012.12); H01L 2224/48227 (2012.12); H01L 2224/73215 (2012.12); H01L 2224/73265 (2012.12); H01L 2924/1443 (2012.12);
Abstract

A packaged semiconductor device includes one or more semiconductor dies with at least one MRAM die; a package substrate having first and second planar surfaces that are substantially larger than planar surfaces of the semiconductor dies, the first planar surface of the package substrate being disposed adjacent to the semiconductor dies and including a plurality of package bond pads that are electrically connected to the semiconductor dies, the second planar surface of the package substrate including a plurality of solder bumps electrically connected to the package bond pads; and a soft magnetic cap confronting the semiconductor dies and having an edge that extends toward and attaches to the package substrate, thereby encapsulating the semiconductor dies. The package substrate includes first and second outer conductive layers and a soft magnetic layer interposed between and separated from the first and second outer conductive layers by first and second insulating layers.


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