The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2025

Filed:

Jun. 25, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Xing Jian Cai, Palo Alto, CA (US);

Chi-Te Chen, Folsom, CA (US);

Wei Qian, Folsom, CA (US);

Yihong Yang, Portland, OR (US);

Jue Chen, Los Gatos, CA (US);

Long Wang, El Dorado Hills, CA (US);

Chung-Hao Joseph Chen, Portland, OR (US);

Su Mi Sam, Portland, OR (US);

Srinivas Thota, Folsom, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/20 (2019.12); G05F 1/66 (2005.12); G06F 30/39 (2019.12); H01L 23/50 (2005.12); H01L 23/528 (2005.12);
U.S. Cl.
CPC ...
H01L 23/50 (2012.12); G05F 1/66 (2012.12); G06F 30/20 (2019.12); G06F 30/39 (2019.12); H01L 23/5286 (2012.12);
Abstract

Some embodiments include apparatuses and electrical models associated with the apparatus. One of the apparatuses includes an integrated circuit having a die; a package substrate; first conductive connections coupled between the die and a first side of the package substrate; second conductive connections located on a second side of the package substrate opposite from the first side. The second conductive connections are coupled to the first conductive connections through conductive paths in the package substrate. The first conductive connections and the conductive connections are associated with an S-parameter of an electrical model of the integrated circuit package. The electrical model further includes at least one of a current value associated with a power rail of the integrated circuit package, an impedance target associated with a location at the integrated circuit package, and a mapping associated with the first and second conductive connections.


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