The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2025

Filed:

Jul. 29, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

William K. Waller, Boise, ID (US);

Dhruval J. Patel, Folsom, CA (US);

Xiannan Di, Folsom, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2005.12); G11C 29/14 (2005.12); G11C 29/18 (2005.12); G11C 29/44 (2005.12); G11C 29/12 (2005.12);
U.S. Cl.
CPC ...
G11C 29/4401 (2012.12); G11C 29/14 (2012.12); G11C 29/18 (2012.12); G11C 29/785 (2012.12); G11C 2029/1202 (2012.12);
Abstract

Techniques for repair of a memory die are disclosed. In the illustrative embodiment, a faulty wordline (or bitline) can be remapped to a redundant wordline on the same layer by entering the address of the faulty wordline in a repair table for the layer. If there are more faulty wordlines on a layer than redundant wordlines available on the layer, the faulty wordlines can be remapped to redundant wordlines on a different layer, and the address of the faulty wordline can be placed in a repair table for the different layer. When a memory operation is received, the wordline address for the memory operation is checked against the repair tables to check if it remapped.


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