The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2025

Filed:

Aug. 07, 2023
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Guang Hu, Mountain View, CA (US);

Nicola Ciocchini, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/32 (2005.12); G06F 3/06 (2005.12); G06F 11/07 (2005.12); G11C 16/34 (2005.12); G11C 29/50 (2005.12); G11C 29/52 (2005.12); G11C 29/56 (2005.12);
U.S. Cl.
CPC ...
G11C 29/32 (2012.12); G06F 3/064 (2012.12); G06F 11/076 (2012.12); G11C 16/3404 (2012.12); G11C 16/349 (2012.12); G11C 29/50 (2012.12); G11C 29/52 (2012.12); G11C 29/56008 (2012.12);
Abstract

A memory device includes a memory array and control logic operatively coupled with the memory array to perform operations including maintaining a set of bins, each bin of the set of bins defining a respective grouping of memory arrays based on elapsed time since programming, wherein each bin of the set of bins is assigned a respective read level offset to achieve a bit error rate satisfying a threshold condition for an error correction decoder throughput specification, receiving a request to perform a read operation addressing the memory array, and causing the read operation to be performed based on the set of bins.


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