The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 08, 2025

Filed:

Mar. 19, 2024
Applicant:

Nanya Technology Corporation, New Taipei, TW;

Inventors:

Chih-Wei Huang, New Taipei, TW;

Hsu-Cheng Fan, New Taipei, TW;

En-Jui Li, New Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/27 (2025.01); H01L 21/3213 (2006.01); H10B 12/00 (2023.01); H10D 30/65 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H01L 21/3105 (2006.01);
U.S. Cl.
CPC ...
H10D 64/513 (2025.01); H01L 21/32139 (2013.01); H10B 12/053 (2023.02); H10B 12/34 (2023.02); H10D 30/658 (2025.01); H10D 64/01 (2025.01); H10D 64/027 (2025.01); H10D 84/0135 (2025.01); H10D 84/038 (2025.01); H01L 21/31058 (2013.01); H10B 12/00 (2023.02);
Abstract

A semiconductor structure includes a substrate, an isolation layer, a dielectric layer, an insulation layer, a conductor and a capping layer. The substrate has a concave portion. The isolation layer is located on a top surface of the substrate. The dielectric layer is located on the isolation layer. The insulation layer is located on a surface of the concave portion and extends to a sidewall of the isolation layer. The conductor is located on the insulation layer in the concave portion. The conductor has a first top surface and a second top surface, and the first top surface is closer to the dielectric layer than the second top surface. The capping layer is located in the concave portion and covers the conductor.


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