The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 08, 2025

Filed:

Nov. 21, 2022
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Kuo-Chih Lai, Tainan, TW;

Shih-Min Chou, Tainan, TW;

Nien-Ting Ho, Tainan, TW;

Wei-Ming Hsiao, Tainan, TW;

Li-Han Chen, Tainan, TW;

Szu-Yao Yu, Tainan, TW;

Chung-Yi Chiu, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/80 (2025.01); H10D 30/01 (2025.01); H10D 30/60 (2025.01); H10D 62/13 (2025.01); H10D 62/17 (2025.01); H10D 62/83 (2025.01); H10D 64/27 (2025.01);
U.S. Cl.
CPC ...
H10D 62/882 (2025.01); H10D 30/01 (2025.01); H10D 30/60 (2025.01); H10D 62/151 (2025.01); H10D 62/235 (2025.01); H10D 62/8303 (2025.01); H10D 64/513 (2025.01);
Abstract

A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.


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