The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 08, 2025

Filed:

Jul. 12, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Jie Chen, New Taipei, TW;

Hsien-Wei Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/07 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/072 (2013.01); H01L 23/3114 (2013.01); H01L 23/3121 (2013.01); H01L 23/5384 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01); H01L 24/73 (2013.01); H01L 25/50 (2013.01); H01L 2224/0401 (2013.01);
Abstract

A semiconductor package includes a first chip package including a plurality of first semiconductor dies and a first insulating encapsulant, a second semiconductor die, a third semiconductor die, and a second insulating encapsulant. The plurality of first semiconductor dies are electrically connected to each other, and the first insulating encapsulant encapsulates the plurality of first semiconductor dies. The second semiconductor die and the third semiconductor die are electrically communicated to each other by connecting to the first chip package, wherein the first chip package is stacked on the second semiconductor die and the third semiconductor die. The second insulating encapsulant encapsulates the first chip package, the second semiconductor die, and the third semiconductor die.


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