The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 08, 2025

Filed:

Jan. 31, 2023
Applicant:

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Inventors:

Théophile Dubreuil, Grenoble, FR;

Paul Amari, Grenoble, FR;

Sylvain Barraud, Grenoble, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/418 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
G11C 13/004 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01);
Abstract

An in-memory computing circuit includes a plurality of memory planes. Each plane forming a two-dimensional matrix of non-volatile, resistive and programmable memory cells. Each memory cell having a selection node, a first input/output node and a second input/output node. The computing circuit comprising at least one elementary group of memory cells comprising: a first memory cell belonging to any one of the memory planes and intended to store a first input datum; a second memory cell belonging to any one of the memory planes and intended to store a second input datum; a third memory cell belonging to a memory plane different from that of the first and of the second memory cell. The third memory cell being intended to store the result of a first logic operation with the first and second input data as operands.


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