The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 08, 2025

Filed:

Sep. 16, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Vinit Mathew Abraham, Hillsboro, OR (US);

Anand K. Enamandram, Folsom, CA (US);

Eswaramoorthi Nallusamy, Cedar Park, TX (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); G06F 9/30 (2018.01); G06F 9/4401 (2018.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 9/5066 (2013.01); G06F 9/30101 (2013.01); G06F 9/4406 (2013.01); G06F 13/4221 (2013.01); G06F 2213/0026 (2013.01);
Abstract

A first plurality of integrated circuit blocks of a first chip are connected to a second plurality of integrated circuit blocks of a second chip. A cluster remapping table is provided on the second chip and is to be programmed to identify a desired asymmetric topology of the connections between the first plurality of integrated circuit blocks and the second plurality of integrated circuit blocks. Logic is to discover the actual topology of the connections between the first plurality of integrated circuit blocks and the second plurality of integrated circuit blocks and determine whether the actual topology matches the desired topology as described in the cluster remapping table.


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