The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 08, 2025

Filed:

Nov. 14, 2023
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Abhijeet Ashok Chachad, Plano, TX (US);

Naveen Bhoria, Plano, TX (US);

David Matthew Thompson, Dallas, TX (US);

Neelima Muralidharan, Murphy, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0808 (2016.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/46 (2006.01); G06F 9/54 (2006.01); G06F 11/30 (2006.01); G06F 12/0811 (2016.01); G06F 12/0815 (2016.01); G06F 12/0817 (2016.01); G06F 12/0831 (2016.01); G06F 12/084 (2016.01); G06F 12/0895 (2016.01); G06F 12/128 (2016.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0811 (2013.01); G06F 9/3004 (2013.01); G06F 9/30047 (2013.01); G06F 9/30079 (2013.01); G06F 9/3867 (2013.01); G06F 9/467 (2013.01); G06F 9/544 (2013.01); G06F 9/546 (2013.01); G06F 11/3037 (2013.01); G06F 12/0808 (2013.01); G06F 12/0815 (2013.01); G06F 12/0828 (2013.01); G06F 12/0831 (2013.01); G06F 12/084 (2013.01); G06F 12/0895 (2013.01); G06F 12/128 (2013.01); G06F 13/1668 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/608 (2013.01);
Abstract

A method includes determining, by a level one (L1) controller, to change a size of a L1 main cache; servicing, by the L1 controller, pending read requests and pending write requests from a central processing unit (CPU) core; stalling, by the L1 controller, new read requests and new write requests from the CPU core; writing back and invalidating, by the L1 controller, the L1 main cache. The method also includes receiving, by a level two (L2) controller, an indication that the L1 main cache has been invalidated and, in response, flushing a pipeline of the L2 controller; in response to the pipeline being flushed, stalling, by the L2 controller, requests received from any master; reinitializing, by the L2 controller, a shadow L1 main cache. Reinitializing includes clearing previous contents of the shadow L1 main cache and changing the size of the shadow L1 main cache.


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