The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 01, 2025

Filed:

Jun. 16, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Yu-Feng Yin, Hsinchu, TW;

Tai-Yen Peng, Hsinchu, TW;

An-Shen Chang, Jubei, TW;

Qiang Fu, Hsinchu, TW;

Chung-Te Lin, Taiwan, TW;

Han-Ting Tsai, Kaoshiung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10N 50/10 (2023.01); H01L 23/528 (2006.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/80 (2023.01);
U.S. Cl.
CPC ...
H10N 50/10 (2023.02); H01L 23/5283 (2013.01); H10B 61/22 (2023.02); H10N 50/01 (2023.02); H10N 50/80 (2023.02);
Abstract

A memory array device includes an array of memory cells located over a substrate, a memory-level dielectric layer laterally surrounding the array of memory cells, and top-interconnection metal lines laterally extending along a horizontal direction and contacting a respective row of top electrodes within the memory cells. Top electrodes of the memory cells are planarized to provide top surfaces that are coplanar with the top surface of the memory-level dielectric layer. The top-interconnection metal lines do not extend below the horizontal plane including the top surface of the memory-level dielectric layer, and prevent electrical shorts between the top-interconnection metal lines and components of memory cells.


Find Patent Forward Citations

Loading…