The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 01, 2025
Filed:
Aug. 23, 2022
Sambanova Systems, Inc., Palo Alto, CA (US);
Ram Sivaramakrishnan, San Jose, CA (US);
Mark Luttrell, Cedar Park, TX (US);
Sumti Jairath, Santa Clara, CA (US);
Raghu Prabhakar, San Jose, CA (US);
Gregory Frederick Grohoski, Bee Cave, TX (US);
SambaNova Systems, Inc., Palo Alto, CA (US);
Abstract
A tile of an embodiment of a coarse-grain reconfigurable architecture (CGRA) is based on an array of fused compute-memory units (FCMUs), pattern memory units (PMUs), and/or pattern compute units (PCUs) arranged in two dimensions, M×N. Unless clearly noted from context, any reference to a FCMU, PCU, or PMU may refer to one or more of the other units. The communication between a set of FCMUs is performed over a (M+1)×(N+1) switch fabric called the array-level network (ALN) where each switch has connections to its neighboring FCMUs and to neighboring switches in each of the four directions.