The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 01, 2025

Filed:

Dec. 29, 2023
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Kamal M. Karda, Boise, ID (US);

Karthik Sarpatwari, Boise, ID (US);

Haitao Liu, Boise, ID (US);

Durai Vishak Nirmal Ramaswamy, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 99/00 (2023.01); H01L 27/12 (2006.01); H01L 29/24 (2006.01); H01L 29/786 (2006.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1225 (2013.01); H01L 27/124 (2013.01); H01L 27/1251 (2013.01); H01L 29/24 (2013.01); H01L 29/78672 (2013.01); H01L 29/7869 (2013.01); H01L 29/7881 (2013.01);
Abstract

Some embodiments include apparatuses and methods using a substrate, a pillar having a length perpendicular to the substrate, a first conductive plate, a second conductive plate, a memory cell located between the first and second conductive plates and electrically separated from the first and second conductive plates, and a conductive connection. The first conductive plate is located in a first level of the apparatus and being separated from the pillar by a first dielectric located in the first level. The second conductive plate is located in a second level of the apparatus and being separated from the pillar by a second dielectric located in the second level. The memory cell includes a first semiconductor material located in a third level of the apparatus between the first and second levels and contacting the pillar and the conductive connection, and a second semiconductor material located in a fourth level of the apparatus between the first and second levels and contacting the pillar.


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