The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 01, 2025

Filed:

Nov. 25, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Susheel Jadhav, Chandler, AZ (US);

Kenneth Brown, Tempe, AZ (US);

David Hui, Santa Clara, CA (US);

Ling Liao, Fremont, CA (US);

Syed S. Islam, Cupertino, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); G02B 6/42 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2023.01);
U.S. Cl.
CPC ...
H01L 23/5381 (2013.01); G02B 6/423 (2013.01); G02B 6/4268 (2013.01); G02B 6/4274 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01);
Abstract

Embodiments described herein may be related to apparatuses, processes, and techniques related to packages that include CPUs and PICs electrically coupled via an interconnect bridge. In embodiments, the PIC are electrically coupled with the EMIB using a fan out RDL to extend reach of the PIC electrical connectors. EICs may be electrically coupled between the PIC and the interconnect bridge. The CPUs may be CPUS, graphical processing units (GPUs), field programmable gate arrays (FPGAs), or other processors. Other embodiments may be described and/or claimed.


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